Solid state image sensors normally include an array of pixels arranged in rows and columns which form a bi-dimensional image representation. An image is read out, row by row, via an array of Analog to Digital Converters (ADC). Every pixel in a column of data is read out by the same ADC. As a result of process mismatch, the pixel data read out from a single column may have an associated offset with respect to its neighbors. Since this fixed offset will be apparent in every pixel read out by that ADC, i.e. a column of data, the resulting image artifact is commonly known as Vertical Fixed Pattern Noise (VFPN) or Fixed Pattern Noise (FPN).
One approach which has been used in the known systems to adjust the resulting image is to counteract the effect of VFPN with a cancellation mechanism.
U.S. Patent Application 2005/0104981 (the disclosure of which is hereby incorporated by reference) discloses a method for correcting column FPN in image sensors including an output circuit for each column for reading pixel image signals by means of a pair of sample capacitors and a switching circuit operable based upon pixel switches for applying pixel voltages to the pair of sample capacitors. Each column has an optically masked pixel which does not contribute to the image but is used to estimate the column FPN. An image processing circuit records the column FPN for each column from the optically masked pixels, records the image signal from the sensor array of active pixels and subtracts the column FPN column-wise from the image signal.
The technique discussed in U.S. Patent Application 2005/0104981 will remove from the correction data, for a sensor employing a Sample and Hold readout methodology, the temporal noise contribution of the pixel but it will not account for temporal noise associated with ADC circuitry. For a continuous time system, which performs an auto-zero operation on the black value and then maintains a continuous connection to the pixel to convert the signal component to a digital code, this methodology is not useful: there is no CDSSIG (Correlated Double Sampling SIGnal) pulse to remove. Removing the TG pulse will allow the reset noise contribution to be removed but noise from the source follower (dominated by Random Telegraphic Signal (RTS) noise and 1/f noise) in addition to other noise, including noise from the ADC, will remain.
With the approach described in U.S. Patent Application 2005/0104981 some noise contributions are stored in the correction data, including temporal noise from the comparator and kTC noise: these noise contributions will be added to pixels from the visible array and will introduce new Vertical Fixed Pattern noise components. Also the described method is specific to a sample and hold readout methodology, and cannot be fully applied to a continuous time architecture.
In order to efficiently bias ADC circuitry and to include an Analog Binning switch implementation to enable Bayer-Scaling, a block of circuitry over multiple columns may be used. Analog Binning is a known technique which allows a number of pixel outputs to be averaged on a capacitive network at the input of a single ADC. Bayer scaling is a technique to average pixel outputs within the red, green and blue Bayer Pattern. Bayer Scaling enables the read out, at high speed, of a reduced sized frame of data with lower noise than would be possible with a basic sub-sampling approach. Design features such as Bayer Scaling switch networks and biasing schemes across multiple columns could cause slight differences from the column to column layout and this can result in column to column offsets which follow a periodic pattern across the array.
There is a need in the art to overcome at least some of the foregoing problems.